The present invention relates generally to digital graphic display processors, and more particularly, to a programmable integrated hardware multiprocess scheduler that forms a working part of a graphics rendering processor.
Real time digital electronic displays are used in many applications such as military command and control workstations and air-traffic control systems. In these displays, the displayed information typically comprises real-time processed data generated by a host processor adapted to receive the basic real-time information from one or more radars, communications systems and/or other data processors. These data are combined with one or more graphic primitives, such as a circle, ellipse or polygon, along with generated alphanumerics, mask areas and texture patterns to provide a relatively easily understood comprehensive graphic display on an output device such as cathoderay tube. In contemporary systems, the various components of the graphics display such as the graphic primitives, mask windows, fill texturing and the like are provided either by a general purpose computer based graphics generator or by a hardware specific graphics generator. Of these, general purpose graphics generators offer system versatility but usually must sacrifice some degree of system performance for ease of programming. On the other hand, hardware specific graphics generators, called cogenerators, provide good system performance.
Increasing demands on military command and control systems, military and civil air-traffic control systems and the like have created a need for high performance graphics cogenerators which, in addition, provide a versatile and easily implemented programming capability. One feature in such a cogenerator is the ability to process a multiplicity of graphics generating needs for symbols, data and graphics figures quickly and easily. In many contemporary graphics cogenerators, such generation is accomplished with a set of software controlled subsystems, each of which must be individually preprogrammed to provide the necessary output information. In such a case the programmer is required to create a routine which initializes and controls the hardware throughout the operation, often interacting on a word by word basis. Furthermore, many single chip processors of the prior art utilize microcoded architectures that, while facilitating testing, are much more sequentially oriented.
There has heretofore been a need for an integrated hardward scheduler that efficiently and effective controls the operation of independently operating subsystems in parallel, with such operations requiring minimum input from the system operator.